1. Field of the Invention
This invention relates to multi-master digital computer systems. More particularly, it relates to such systems that provide pipelining of a requesting device onto a bus ms a master while the current master device is still accessing the bus.
2. Description of the Prior Art
In modern computer systems, a bus is commonly used to interconnect the various elements comprising the system to one another for the transfer of information carrying signals therebetween. For example, a central processor is typically connected to various memory devices and input/output devices via a bus structure to carry the signals necessary for the operation of each element of the system. Signals carried by the bus may include, for example, address signals, data signals, clock signals and other control signals. The bus must efficiently transmit such signals to all of the elements of the computer system connected to it for the intended functions and operations of the system to be carried out.
One of the principal indicia by which a computer system is judged is its speed of operation and therefore the volume of data which it can process in a given period of time. Because the bus is utilized in virtually every operation performed by the computer system, it is a key component whose operational characteristics have a tremendous effect on the overall performance of the computer system. For example, the speed of the computer system is limited to a large degree by the rate at which the bus is capable of responding to a series of commands and transferring data between one element and another.
One technique which has been used to increase the speed of data handling within a computer system is that of pipelining, which is the sequential writing of a plurality of data words onto a bus without receiving an acknowledgement that any of the words have been read out at their destination elements. For example, the burst mode data transfer of data by writing a word from one location to another along a bus upon the occurrence of each successive clock cycle is an example of pipelining.
Various forms of pipelining in the prior computer art are well known. For example, large scale vector machines have utilized pipelining of data into the registers, adders, and output buffers to save time. That is, data is entered into the first of a series of operational registers while the remaining registers have other data in them.
Also, address pipelining in single processor systems is used to increase bus efficiency in the prior art. In such a pipeline system, the master generates the address for the next cycle before the data for the current cycle has been transferred. In this manner, the slave can be decoding the address before the actual start of the cycle.
The advent of computer systems with multiple processors has greatly increased the speed with which complex data processing functions can be performed. In such prior art computers, a plurality of processors share common elements such as system memory, input/output devices, and bus structures. Both processors are capable of serving as a bus master to control the transfer of information to and from a slave device via the system bus. Although both processors can be performing computations simultaneously, only one can be a bus master at a time. Each processor must request the bus, be granted access to it to become the bus master, complete the intended transaction and then relinquish the bus and make it available to another bus master.
With respect to prior art multi-master systems, such as computer systems with multiple processors, when a current bus master is to give control of the bus to a requesting device, it will complete its current cycle before permitting the requesting device access to the bus as a master as indicated above. However, in U.S. Pat. No. 4,837,736 to Donaldson et al there is disclosed a multi-master system in which an uncompleted transaction by a bus master can be temporarily interrupted to allow bus cycles to be utilized by other bus masters in the interim period. For example, in Donaldson, a device to which a command transfer is directed by a bus master may not be able to return the requested data immediately and cycles by other devices are allowed on the bus between the command transfer and the return data transfer of the read transaction. While such a configuration may avoid periodic inadvertent interruptions of access to the bus during entire transactions, it does not permit an orderly optimization of the data transfer rates within a multi-master computer system by allowing two master devices to access a single bus at the same time.
The present invention extends the benefits of pipelining to multi-master systems. The current master relinquishes control of the bus in stages. This permits the requesting device to access the bus as a master and address the desired slave before the current master has given up control of the bus. In a multiprocessor system, where the bus is constantly accessed by different devices, a considerable performance increase is achieved.